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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78011H, 78012H, 78013H, 78014H
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD78011H, 78012H, 78013H, and 78014H are the products in the PD78014H subseries within the 78K/0 series. Compared with the older PD78018F subseries, this subseries reduces the EMI (Electro Magnetic Interface) noise generated from the microcontroller. Functions are described in detail in the following User's Manual, which should be read when carring out design work. PD78014H Subseries User's Manual: Planned to publish 78K/0 Series User's Manual - Instruction: IEU-1372
FEATURES
* Low EMI noise model * Large on-chip ROM & RAM
Item Product Name
Program Memory (ROM) 8K bytes 16K bytes 24K bytes 32K bytes
Data Memory Internal HighSpeed RAM 512 bytes Internal Buffer RAM 32 bytes Package * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 14 mm) 1024 bytes * 64-pin plastic LQFP (12 x 12 mm)
PD78011H PD78012H PD78013H PD78014H
* * * * * * *
External memory expansion space : 64K bytes Instruction execution time can be varied from high-speed (0.4 s) to ultra-low-speed (122 s) I/O ports: 53 (N-ch open-drain : 4) 8-bit resolution A/D converter : 8 channels Serial interface : 2 channels Timer : 5 channels Supply voltage : VDD = 1.8 to 5.5 V
APPLICATION FIELD
Cellular phone, pager, VCR, audio, camera, home appliances, etc.
The information in this document is subject to change without notice. Document No. U11898EJ1V0DS00 (1st edition) Date Published January 1997 N Printed in Japan
(c)
1997
PD78011H, 78012H, 78013H, 78014H
ORDERING INFORMATION
Part Number Package 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic shrink DIP (750 mil) QFP (14 x 14 mm) LQFP (12 x 12 mm) shrink DIP (750 mil) QFP (14 x 14 mm) LQFP (12 x 12 mm) shrink DIP (750 mil) QFP (14 x 14 mm) LQFP (12 x 12 mm) shrink DIP (750 mil) QFP (14 x 14 mm) LQFP (12 x 12 mm)
PD78011HCW-xxx PD78011HGC-xxx-AB8 PD78011HGK-xxx-8A8 PD78012HCW-xxx PD78012HGC-xxx-AB8 PD78012HGK-xxx-8A8 PD78013HCW-xxx PD78013HGC-xxx-AB8 PD78013HGK-xxx-8A8 PD78014HCW-xxx PD78014HGC-xxx-AB8 PD78014HGK-xxx-8A8
Remark xxx indicates ROM code No.
2
PD78011H, 78012H, 78013H, 78014H
DEVELOPMENT OF 78K/0 SERIES The following products are available in the 78K/0 series. The parts numbers enclosed in a frame are subseries names.
Products under mass production Products under development The Y subseries supports the I2C bus. For control applications 100 pins 100 pins 100 pins 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins 42/44 pins
PD78078 PD78070A PD780018
Note
PD78078Y PD78070AY PD780018Y
Note
Adds timer to PD78054 and reinforces external interface function ROM-less model of PD78078 Reinforces serial I/O of PD78078 and limits functions Low EMI noise model of PD78054 Adds UART and D/A to PD78014 and reinforces I/O Reinforces A/D of PD780024 Reinforces serial I/O of PD78018F. Low EMI noise model Reinforces A/D of PD780924 UART as inverter control circuit. Low EMI noise model Low EMI noise model of PD78018F
PD78058F PD78054 PD780034 PD780024 PD780964 PD780924 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083
PD78058FY PD78054Y PD780034Y PD780024Y
PD78018FY PD78014Y PD78002Y
Low voltage (1.8 V) model of PD78014 with many variations of ROM and RAM Adds A/D and 16-bit timer to PD78002 Adds A/D to PD78002 Basic subseries for control applications UART. Low voltage (1.8 V) model
For FIPTM driving 100 pins 80 pins 78K/0 series 64 pins
PD780208 PD78044F PD78024
For LCD driving
Reinforces I/O and FIP C/D of PD78044F. Total display outputs : 53 pins Adds 6-bit U/D counter to PD78024. Total display outputs : 34 pins Basic subseries for FIP driving. Total display outputs : 26 pins
100 pins 100 pins 100 pins
PD780308 PD78064B PD78064
PD780308Y PD78064Y
Reinforces SIO of PD78064 with expanded ROM and RAM Low EMI noise model of PD78064 Basic subseries for LCD driving. UART
Supporting IEBusTM 80 pins
PD78098
Adds IEBus controller to PD78054
For LV 64 pins
PD78P0914
PWM output, LV digital code decoder, and Hsync counter
Note Under planning
3
PD78011H, 78012H, 78013H, 78014H
The major differences between the respective subseries are shown below.
Functions Subseries For Control Timer 8-bit 16-bit Watch WDT 4ch 1ch 1ch 1ch VDD MIN. Value 1.8 V 2.7 V
ROM Capacity 32 K-60 K - 48 K-60 K
8-bit 10-bit 8-bit A/D A/D D/A 8ch -- 2ch --
Serial Interface
I/O
External Expansion
PD78078 PD78070A PD780018
PD78058F PD78054 PD780034 PD780024
2ch 16 K-60 K 8 K-32 K -- 8ch 8ch --
2ch --
3ch (UART: 1ch) 88 61 2chs 88 (time-division 3-wire: 1 ch) 3ch (UART: 1ch) 69
pins pins pins
pins 2.0 V 1.8 V
For FIP driving For LCD driving
PD780964 PD780924 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083 PD780208 PD78044F PD78024 PD780308
3ch 2ch 8 8 8 8 K-60 K K-32 K K K-16 K K-60 K-40 K-32 K-60 K K K K 2ch
Note 1ch
-- 1ch
-- 8ch
8ch --
3chs 51 pins (UART: 1 ch, time-division 3-wire: 1 ch) 2ch (UART: 2ch) 47 pins 2ch 53 pins
2.7 V 1.8 V 2.7 V
--
32 16 24 48
1ch
-- 1ch -- 1ch
1ch -- 8ch 8ch
1ch
--
--
2ch
1ch
1ch
1ch
8ch
--
--
IEBus support For LV
PD78064B PD78064 PD78098
32 K 16 K-32 K 32 K-60 K
39 53 1ch (UART: 1ch) 33 2ch 74 68 54 3ch 57 (time-division UART: 1 ch) 2ch (UART: 1ch)
pins pins pins pins pins pins pins
-- 1.8 V 2.7 V -- --
1.8 V
--
2.0 V 2.7 V 4.5 V
2ch 6ch
1ch --
1ch --
1ch 1ch
8ch 8ch
-- --
2ch --
3ch (UART: 1ch) 69 pins 2ch 54 pins
PD78P0914 32 K
Note 10-bit timer: 1 channel
4
PD78011H, 78012H, 78013H, 78014H
OVERVIEW OF FUNCTION
Item Product Name ROM High-speed RAM Buffer RAM
PD78011H
8K bytes 512 bytes 32 bytes 64K bytes
PD78012H
16K bytes
PD78013H
24K bytes 1024 bytes
PD78014H
32K bytes
Internal memory
Memory space General-purpose registers Instruction cycle When main system clock selected When subsystem clock selected Instruction set
8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip instruction execution time cycle modification function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 10.0 MHz operation) 122 s (at 32.768 kHz operation) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits,16 bits / 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. : 53 : 02 : 47 : 04
I/O ports
Total * CMOS input * CMOS I/O * N-channel open-drain I/O (15 V withstand voltage)
A/D converter
* 8-bit resolution x 8 channels * Operable over a wide power supply voltage range: AVDD = 1.8 to 5.5 V * 3-wire serial I/O/SBI /2-wire serial I/O mode selectable: 1 channel * 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel * * * * 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer : : : : 1 2 1 1 channel channels channel channel
Serial interface
Timer
Timer output Clock output
3 (14-bit PWM output x 1) 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock: 10.0 MHz operation), 32.768 kHz (at subsystem clock: 32.768 kHz operation) 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: 10.0 MHz operation) Internal Internal 1 Internal : 1, External : 1 : 8, External : 4 :1
Buzzer output Vectored interrupt sources Test input Supply voltage Operating ambient temperature Package Maskable Non-maskable Software
VDD = 1.8 to 5.5 V TA = -40 to +85C * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic LQFP (12 x 12 mm)
5
PD78011H, 78012H, 78013H, 78014H
TABLE OF CONTENTS
1. 2. 3. PIN CONFIGURATION (Top View) ......................................................................................................... 7 BLOCK DIAGRAM ................................................................................................................................... 10 PIN FUNCTIONS ...................................................................................................................................... 11
3.1 PORT PINS ........................................................................................................................................................ 11 3.2 OTHER PORTS ................................................................................................................................................. 12 3.3 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS ................................................ 14
4. 5.
MEMORY SPACE .................................................................................................................................... 16 PERIPHEL HARDWARE FUNCTION FEATURES ................................................................................ 17
5.1 5.2 5.3 5.4 5.5 5.6 5.7 PORTS ............................................................................................................................................................... CLOCK GENERATOR ....................................................................................................................................... TIMER/EVENT COUNTER ................................................................................................................................ CLOCK OUTPUT CONTROL CIRCUIT ............................................................................................................ BUZZER OUTPUT CONTROL CIRCUIT ........................................................................................................... A/D CONVERTER .............................................................................................................................................. SERIAL INTERFACES ...................................................................................................................................... 17 18 19 21 21 22 23
6.
INTERRUPT FUNCTIONS AND TEST FUNCTIONS .............................................................................. 25
6.1 INTERRUPT FUNCTIONS ................................................................................................................................. 25 6.2 TEST FUNCTIONS ............................................................................................................................................ 28
7. 8. 9.
EXTERNAL DEVICE EXPANTION FUNCTIONS ................................................................................... 29 STANDBY FUNCTIONS ........................................................................................................................... 29 RESET FUNCTIONS ................................................................................................................................ 29
10. INSTRUCTION SET ................................................................................................................................. 30 11. ELECTRICAL SPECIFICATIONS ............................................................................................................ 33 12. PACKAGE DRAWINGS ........................................................................................................................... 57 13. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 60 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 62 APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 64
6
PD78011H, 78012H, 78013H, 78014H
1. PIN CONFIGURATION (Top View)
* 64-Pin Plastic Shrink DIP (750 mil)
PD78011HCW-xxx, 78012HCW-xxx, 78013HCW-xxx, 78014HCW-xxx
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVREF AVDD P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 IC X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P63 P62 P61 P60 P57/A15 P56/A14
Cautions 1. Always connect the IC (Internally Connected) pin to VSS directly. 2. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an application where the noise generated from the microcontroller must be reduced, connect the AVDD pin to a power supply of the same voltage as VDD. 3. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an application where the noise generated from the microcontroller must be reduced, connect AVSS pin to a ground line separate from VSS.
7
PD78011H, 78012H, 78013H, 78014H
* 64-Pin Plastic QFP (14 x 14 mm) PD78011HGC-xxx-AB8, 78012HGC-xxx-AB8, 78013HGC-xxx-AB8, 78014HGC-xxx-AB8 * 64-Pin Plastic LQFP (12 x 12 mm) PD78011HGK-xxx-8A8, 78012HGK-xxx-8A8, 78013HGK-xxx-8A8, 78014HGK-xxx-8A8
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P27/SCK0
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
64 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P12/ANI2
P21/SO1
P23/STB
P20/SI1
AVREF
AVDD
P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 IC X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33 32
P56/A14
P57/A15
P60
P61
P62
P63
P64/RD
P47/AD7
P52/A10
P53/A11
P54/A12
P55/A13
Cautions 1. Always connect the IC (Internally Connected) pin to VSS directly. 2. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an application where the noise generated from the microcontroller must be reduced, connect the AVDD pin to a power supply of the same voltage as VDD. 3. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an application where the noise generated from the microcontroller must be reduced, connect AVSS pin to a ground line separate from VSS.
8
P65/WR
P50/A8
P51/A9
VSS
PD78011H, 78012H, 78013H, 78014H
A8-A15 AD0-AD7 ANI0-ANI7 ASTB AVDD AVREF AVSS BUSY BUZ IC INTP0-INTP3 P00-P04 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57
: Address Bus : Address/Data Bus : Analog Input : Address Strobe : Analog Power Supply : Analog Reference Voltage : Analog Ground : Busy : Buzzer Clock : Internally Connected : Interrupt from Peripherals : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5
P60-P67 PCL RD RESET SB0, SB1 SCK0, SCK1 SI0, SI1 SO0, SO1 STB TI0-TI2 TO0-TO2 VDD VSS WAIT WR X1, X2 XT1, XT2
: Port 6 : Programmable Clock : Read Strobe : Reset : Serial Bus : Serial Clock : Serial Input : Serial Output : Strobe : Timer Input : Timer Output : Power Supply : Ground : Wait : Write Strobe : Crystal (Main System Clock) : Crystal (Subsystem Clock)
9
PD78011H, 78012H, 78013H, 78014H
2. BLOCK DIAGRAM
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
P00 PORT0 P01-P03 P04
8-bit TIMER/ EVENT COUNTER 1
PORT1
P10-P17
8-bit TIMER/ EVENT COUNTER 2
PORT2
P20-P27
WATCHDOG TIMER
PORT3
P30-P37
WATCH TIMER 78K/0 CPU CORE SERIAL INTERFACE 0 ROM
PORT4
P40-P47
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SERIAL INTERFACE 1
PORT5
P50-P57
PORT6
P60-P67 AD0/P40AD7/P47 A8/P50A15/P57
RAM ANI0/P10ANI7/P17 A/D CONVERTER AVREF
EXTERNAL ACCESS
RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET
INTP0/P00INTP3/P03
INTERRUPT CONTROL
X1 SYSTEM CONTROL X2 XT1 XT2
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT CONTROL
VDD VSS AVDD AVSS IC
Remark Internal ROM & RAM capacity varies depending on the product.
10
PD78011H, 78012H, 78013H, 78014H
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Pin Name P00 P01 P02 P03 P04Note 1 P10 to P17 Input Input/ output Input only Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.Note 2 Port 2 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input Input I/O Input Input/ output Port 0 5-bit I/O port Input only Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Function On Reset Input Input DualFunction Pin INTP0/TI0 INTP1 INTP2 INTP3 XT1 ANI0 to ANI7
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
Input/ output
Input
SI1 SO1 SCK1 STB BUSY SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 3 8-bit input/output port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistor can be used by software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Input/ output
Port 4 8-bit input/output port. Input/output can be specified in 8-bit unit. When used as an input port, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
Notes 1. When using the P04/XT1 pin as an input port pin, set bit 6 (FRC) of the processor clock control register (PCC) to 1 (do not use the internal feedback resistor of the subsystem clock oscillation circuit). 2. When using the P10/ANI0 through P17/ANI7 pins as the analog input pins of the A/D converter, the internal pull-up resistors are automatically not used.
11
PD78011H, 78012H, 78013H, 78014H
3.1 PORT PINS (2/2)
Pin Name P50 to P57 I/O Input/ output Function Port 5 8-bit input/output port. LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 6 8-bit input/output port. Input/output can be specified bit-wise. N-ch open-drain input/output port. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. On Reset Input DualFunction Pin A8 to A15
P60 P61 P62 P63 P64 P65 P66 P67
Input/ output
Input
When used as an input port, on-chip pull-up resistor can be used by software.
RD WR WAIT ASTB
Caution Do not manipulate the pins multiplexed with a port pin as follows during A/D conversion; otherwise, the rated total error during A/D conversion may not be satisfied. <1> Rewriting the contents of the output latch when the pin is used as an output port pin. <2> Changing the output level of the pin used as an output pin even when the pin is not used as a port pin. 3.2 OTHER PORTS (1/2)
Pin Name INTP0 INTP1 INTP2 INTP3 SI0 SI1 SO0 SO1 SB0 SB1 SCK0 SCK1 STB BUSY Input /output Input /output Output Input Serial interface serial data input/output. Input Output Serial interface serial data output. Input Input I/O Input Function External interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. Falling edge detection external interrupt request input. Serial interface serial data input. Input On Reset Input DualFunction Pin P00/TI0 P01 P02 P03 P25/SB0 P20 P26/SB1 P21 P25/SI0 P26/SO0 Serial interface serial clock input/output. Input P27 P22 Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Input Input P23 P24
12
PD78011H, 78012H, 78013H, 78014H
3.2 OTHER PORTS (2/2)
DualFunction Pin P00/INTP0 P33 P34 Input P30 P31 P32 Input Input Input Input Input P35 P36 P40 to P47 P50 to P57 P64 P65 Input Input P66 P67
Pin Name TI0 TI1 TI2 TO0 TO1 TO2 PCL BUZ AD0 to AD7 A8 to A15 RD WR WAIT ASTB
I/O Input
Function External count clock input to 16-bit timer (TM0). External count clock input to 8-bit timer (TM1). External count clock input to 8-bit timer (TM2).
On Reset Input
Output
16-bit timer (TM0) output (multiplexed with 14-bit PWM output). 8-bit timer (TM1) output. 8-bit timer (TM2) output.
Output Output Input /output Output Output
Clock output (for main system clock, subsystem clock trimming). Buzzer output. Low-order address/data bus at external memory expansion. High-order address bus at external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Output
Wait insertion at external memory access. Strobe output which latches the address information output at port 4 and port 5 to access external memory. A/D converter analog input. A/D converter reference voltage input. A/D converter analog power supply (multiplexed with a port power pin). A/D converter ground potential (multiplexed with a port ground pin). System reset input. Main system clock oscillation crystal connection.
ANI0 to ANI7 AVREF AVDD AVSS RESET X1 X2 XT1 XT2 VDD VSS IC
Input Input -- -- Input Input -- Input -- -- -- --
Input -- -- -- -- -- --
P10 to P17 -- -- -- -- -- -- P04 -- -- -- --
Subsystem clock oscillation crystal connection.
Input --
Positive power supply (except port pins). Ground potential (except port pins). Internal connection. Connected to VSS directly.
-- -- --
Cautions 1. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an application where the noise generated from the microcontroller must be reduced, connect the AVDD pin to a power supply of the same voltage as VDD. 2. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an application where the noise generated from the microcontroller must be reduced, connect AVSS pin to a ground line separate from VSS.
13
PD78011H, 78012H, 78013H, 78014H
3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1. Table 3-1. Input/Output Circuit Type of Each Pin
Pin Name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 to P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60 to P63 P64/RD P65/WR P66/WAIT P67/ASTB RESET XT2 AVREF AVDD AVSS IC 2 16 -- Input -- -- Leave open. Connected to VSS . Connected to VDD . Connected to VSS . Connected to VSS directly. 5-O 5-J 13-I 5-J Individually connected to VDD via resistor. Individually connected to VDD or VSS via resistor. Individually connected to VDD via resistor. Individually connected to VDD or VSS via resistor. 5-J 8-D 5-J 16 11-C 8-D 5-J 8-D 5-J 8-D 10-C Input Input/output Connected to VDD or VSS. Individually connected to VDD or VSS via resisitor. Input/output Circuit Type 2 8-D Input Input/output I/O Recommended Connection when Not Used Connected to VSS . Individually connected to VSS via resistor.
14
PD78011H, 78012H, 78013H, 78014H
Figure 3-1. Pin Input/Output Circuits
Type 2 Type 10-C pullup enable IN data open drain output disable AVDD P-ch IN / OUT Schmitt-Triggered Input with Hysteresis Characteristic N-ch AVSS
AVDD P-ch
Type 5-J
pullup enable AVDD data output disable input enable
AVDD P-ch
Type 11-C
pullup enable data
AV DD P-ch AVDD P-ch IN / OUT N-ch P-ch + - AVSS N-ch AVSS VREF (Threshold Voltage)
P-ch IN / OUT N-ch AVSS
output disable Comparator
input enable
Type 5-O AVDD pullup enable data output disable P-ch AVDD P-ch IN / OUT N-ch AVSS
Type 13-I
AVDD Mask Option N-ch AVSS AVDD RD P-ch
IN / OUT
data output disable
Middle-High Voltage Input Buffer
Type 8-D AVDD pullup enable AV DD data output disable P-ch IN / OUT N-ch AVSS Type 16
feedback cut-off
P-ch
P-ch
XT1
XT2
15
PD78011H, 78012H, 78013H, 78014H
4. MEMORY SPACE
The memory map of the PD78011H, 78012H, 78013H, 78014H is shown in Figure 4-1.
Figure 4-1. Memory Map
FFFFH Special Function Registers (SFR) 256 x 8 Bits FF00H FEFFH General-Purpose Registers 32 x 8 Bits FEE0H FEDFH
Internal High-Speed RAMNote
mmmmH mmmmH-1 Use Prohibited FAE0H Data Memory Space FADFH FAC0H FABFH FA80H FA7FH Program Memory Space nnnnH+1 nnnnH Buffer RAM 32 x 8 Bits
nnnnH Program Area 1000H 0FFFH CALLF Entry Area Use Prohibited 0800H 07FFH Program Area External Memory 0080H 007FH CALLT Table Area 0040H 003FH Internal ROMNote Vector Table Area 0000H
0000H
Note
Internal ROM and internal high-speed RAM capacities vary depending on the product (see the table below).
Product Name
Intenal ROM End Address nnnnH 1FFFH 3FFFH 5FFFH 7FFFH
Internal High-Speed RAM Start Address mmmmH FD00H
PD78011H PD78012H PD78013H PD78014H
FB00H
16
PD78011H, 78012H, 78013H, 78014H
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 PORTS The I/O port has the following three types * CMOS input (P00, P04) * CMOS input/output (P01 to P03, port 1 to port 5, P64 to P67) * N-ch open-drain input/output(15V withstand voltage) (P60 to P63) Total : 2
: 47 :4 : 53
Table 5-1. Functions of Ports
Port Name Port 0 Pin Name P00, P04 P01 to P03 Port 1 Port 2 Port 3 Port 4 P10 to P17 P20 to P27 P30 to P37 P40 to P47 Dedicated Input port Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified in 8-bit units. When used as an input port, pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. LED can be driven directly. N-ch open-drain input/output port. Input/output can be specified bit-wise. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Function
Port 5
P50 to P57
Port 6
P60 to P63
P64 to P67
17
PD78011H, 78012H, 78013H, 78014H
5.2 CLOCK GENERATOR There are two types of clock generator: main system clock and subsystem clock. The instruction exection time can be changed. * 0.4s/0.8s/1.6s/3.2s/6.4s (Main system clock: at 10.0 MHz operation) * 122s (Subsystem clock: at 32.768 KHz operation)
Figure 5-1. Clock Generator Block Diagram
XT1/P04 XT2
Subsystem Clock Osicillator
fXT
Watch Timer Clock Output Function Prescaler
X1 X2
Main System Clock Osicillator
fX
Prescaler
Clock to Peripheral Hardware fX 24
fX 2 STOP
fX 22
fX 23
Selector
Standby Control Circuit
Wait Control Circuit
CPU Clock (fCPU)
INTP0 Sampling Clock
18
PD78011H, 78012H, 78013H, 78014H
5.3 TIMER/EVENT COUNTER The following five channels are incorporated in the timer/event counter. * 16-bit timer/event counter * 8-bit timer/event counter * Watch timer * Watchdog timer : 1 channel : 2 channels : 1 channel : 1 channel
Table 5-2. Types and Functions of Timer/Event Counter
16-bit Timer/Event Counter Type Interval timer Externanal event counter Functions Timer output PWM output Pulse width mesurement Sqare wave output Interrupt request Test input 1 channel 1 channel 1 output 1 output 1 input 1 output 2 - 8-bit Timer/Event Counter 2 channels 2 channels 2 outputs - - 2 outputs 2 -
Watch Timer 1 channel - - - - - 1 1
Watchdog Timer 1 channel - - - - - 1 -
Figure 5-2. 16-bit Timer/Enent Counter Block Diagram
Internal Bus
16-Bit Compare Register (CR00) PWM Pulse Output Control Circuit 16-Bit Timer Register (TM0) Clear Selector Output Control Circuit
INTTM0
Match
TO0/P30
fX/2 fX/22 fX/23 TI0/INTP0/P00
Edge Detection Circuit Selector
INTP0 16-Bit Capture Register (CR01)
Internal Bus
19
PD78011H, 78012H, 78013H, 78014H
Figure 5-3. 8-bit Timer/Enent Counter Block Diagram
Internal Bus INTIM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector
Match
Output Control Circuit
TO2/P32 INTTM2
fX/22-fX/210 fX/212 TI1/P33
Selector 8-Bit Timer Register 1 (TM1) Clear Selector 8-Bit Timer Register 2 (TM2) Clear Selector Selector Output Control Circuit Internal Bus
fX/22-fX/210 fX/212 TI2/P34
TO1/P31
Figure 5-4. Watch Timer Block Diagram
fX/28
Selector
Selector
5-Bit Counter
fW 214
Selector INTWT
fW
Prescaler
fXT fW 24 fW 25 fW 26 fW 27 fW 28 fW 29
fW 213
Selector
INTTM3
20
PD78011H, 78012H, 78013H, 78014H
Figure 5-5. Watchdog Timer Block Diagram
fX 24 fX 25 fX 26 fX 27
Prescaler
fX 28
fX 29
fX 210
fX 212
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
5.4 CLOCK OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for clock output. * 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation) * 32.768 kHz (Subsystem clock: at 32.768 kHz operation)
Figure 5-6. Clock Output Control Block Diagram
fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fXT
Selector Synchronization Circuit Output Control Circuit PCL/P35
5.5 BUZZER OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for buzzer output. * 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation)
Figure 5-7. Buzzer Output Control Block Diagram
fX/210 fX/211 fX/212
Selector Output Control Circuit BUZ/P36
21
PD78011H, 78012H, 78013H, 78014H
5.6 A/D CONVERTER The A/D converter has on-chip eight 8-bit resolution channels. There are the following two method to start A/D conversion. * Hardware starting * Software starting
Figure 5-8. A/D Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive Approximation Register (SAR) AVSS Selector Tap Selector Sample & Hold Circuit Voltage Comparator AVDD AVREF
INTP3/P03
Falling Edge Detector
Control Circuit
INTAD INTP3
A/D Conversion Result Register (ADCR)
Internal Bus
Caution Do not manipulate the pins multiplexed with a port pin (refer to 3.1 PORT PINS) during A/D conversion; otherwise, the rated total error during A/D conversion may not be satisfied. <1> Rewriting the contents of the output latch when the pin is used as an output port pin. <2> Changing the output level of the pin used as an output pin even when the pin is not used as a port pin.
22
PD78011H, 78012H, 78013H, 78014H
5.7 SERIAL INTERFACES There are two on-chip clocked serial interfaces as follows. * Serial Interface channel 0 * Serial Interface channel 1 Table 5-3. Type and Function of Serial Interface
Function 3-wire serial I/O mode 3-wire serial I/O mode with automatic data transmit/ receive function SBI (Serial Bus Interface) mode 2-wire serial I/O mode O (MSB-first) O (MSB-first) - - Serial Interface Channel 0 O (MSB/LSB-first switchable) - Serial Interface Channel 1 O (MSB/LSB-first switchable) O (MSB/LSB-first switchable)
Figure 5-9. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
Selector
SO0/SB1/P26
Serial I/O Shift Register 0 (SIO0)
Output Latch
Selector
Bus Release/Command/ Acknowledge Detection Circuit Serial Clock Counter
Busy/Acknowledge Output Circuit
SCK0/P27
Interrupt Request Signal Generator
INTCSI0
fx/22-fx/29
Serial Clock Control Circuit
Selector
TO2
23
PD78011H, 78012H, 78013H, 78014H
Figure 5-10. Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer RAM
SI1/P20
Serial I/O Shift Register 1 (SIO1)
SO1/P21
STB/P23
BUSY/P24
Handshake Control Circuit
SCK/P22
Serial Clock Counter
Interrupt Request Signal Generator
INTCSI1
fX/22 - fX/29
Serial Clock Control Circuit
Selector
TO2
24
PD78011H, 78012H, 78013FH, 78014H
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS There are the 14 interrupt sources of 3 different kind as shown below. * Non-maskable * Maskable * Software : 1
: 12 :1
Table 6-1. Interrupt Source List
Default Priority Note 1 Interrupt Source Name INTWDT Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH Serial interface channel 0 transfer end Serial interface channel 1 transfer end Reference time interval signal from watch timer 16 bit timer/event counter match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation A/D converter conversion end BRK instruction execution - Internal 000EH 0010H 0012H (B) Internal/ External Vector Table Address Basic Configuratin Type Note 2 Internal 0004H (A)
Interrupt Type
Non-maskable
---
Maskable
0
INTWDT
(B)
1 2 3 4 5 6 7
INTP0 INTP1 INTP2 INTP3 INTCSI0 INTCSI1 INTTM3
(C) (D)
8
INTTM0
0014H
9
INTTM1
0016H
10
INTTM2
0018H
11 Software ---
INTAD BRK
001AH 003EH (E)
Notes 1. The default pririty is the priority applicable when more than one maskable interrupt is generated. 0 is the highest priority and 11, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) on the next page.
25
PD78011H, 78012H, 78013H, 78014H
Figure 6-1. Basic Interrupt Function Configuration (1/2)
(A) Internal Non-Maskable Interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(B) Internal Maskable Interrupt
Internal Bus
MK
IE
PR
ISP
Interrupt Request
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(C) External Maskable Interrupt (INTP0)
Internal Bus
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Sampling Clock
Edge Detector
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
26
PD78011H, 78012H, 78013FH, 78014H
Figure 6-1. Basic Interrupt Function Configuration (2/2) (D) External Maskable Interrupt (Except INTP0)
Internal Bus
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Edge Detector
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(E)
Software Interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
IF IE ISP MK PR
: Interrupt request flag : Interrupt enable flag : In-service priority flag : Interrupt mask flag : Priority spcification flag
27
PD78011H, 78012H, 78013H, 78014H
6.2 TEST FUNCTIONS There are two test functions as shown in Table 6-2.
Table 6-2. Test Source List
Test Source Internal/External Name INTWT INTPT4 Trigger Watch timer overflow Port 4 falling edge detection Internal External
Figure 6-2. Test Function Basic Configuration
Internal Bus
MK
Test Input
IF
Standby Release Signal
IF
: Test input flag
MK : Test mask flag
28
PD78011H, 78012H, 78013FH, 78014H
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion function is used to connect external devices to areas other than the internal ROM, RAM and SFR. Ports 4 to 6 are used for connection with external devices.
8. STANDBY FUNCTIONS
There are the following two standby functions to reduce the current dissipation. * HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operat ing mode. * STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates withultra-low power consumption using only the subsystem clock.
Figure 8-1. Standby Functions
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock OperationNote HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply to CPU is stopped, oscillation)
HALT ModeNote (Clock supply to CPU is stopped, oscillation)
Note The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set the MCC to stop the main system clock. The STOP instruction cannot be used.
Caution
When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program.
9. RESET FUNCTIONS
There are the following two reset methods. * External reset input by RESET pin. * Internal reset by watchdog timer runaway time detection.
29
PD78011H, 78012H, 78013H, 78014H
10. INSTRUCTION SET
(1) 8-Bit Instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand #byte 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP r1 sfr sadder MOV MOV DBNZ INC DEC DBNZ MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A r Note sfr saddr !addr16 PSW [DE] [HL] [HL+byte] [HL+B] $adder16 [HL+C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 1 None
ROR ROL RORC ROLC
r
MOV
INC DEC
MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV MOV
!adder16 PSW
PUSH POP
[DE] [HL]
MOV MOV ROR4 ROL4
[HL+byte] [HL+B] [HL+C] X C
MOV
MULU DIVUW
Note Except r=A
30
PD78011H, 78012H, 78013FH, 78014H
(2) 16-Bit Instruction MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand 1st Operand AX #byte ADDW SUBW CMPW rp MOVW MOVWNote INCW, DECW PUSH, POP AX rp Note MOVW XCHW saddrp MOVW !addr16 MOVW SP MOVW None MOVW
sfrp sadderp !adder16 SP
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
Note Only when rp=BC, DE, HL. (3) Bit Manipulation Instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand A.bit 1st Operand A.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 sfr.bit saddr.bit PWS.bit [HL].bit CY $addr16 None
sfr.bit
MOV1
SET1 CLR1
saddr.bit
MOV1
SET1 CLR1
PSW.bit
MOV1
SET1 CLR1
[HL].bit
MOV1
SET1 CLR1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
SET1 CLR1 NOT1
31
PD78011H, 78012H, 78013H, 78014H
(4) Call Instruction/Branch Instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand AX 1st Operand Basic instruction BR CALL, BR CALLF CALLT BR, BC, BNC, BZ, BNZ BT, BF, BTCLR, DBNZ !addr16 !addr11 [addr5] $addr16
Compound instruction
(5) Other Instruction ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
32
PD78011H, 78012H, 78013H, 78014H
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Symbol VDD AVDD AVREF AVSS Input voltage VI1 VI2 Output voltage Analog input voltage Output current high VO VAN P10 to P17 1 pin IOH P10 to P17, P20 to P27, P30 to P37 total P01 to P03, P40 to P47, P50 to P57, P60 to P67 total Output current low Peak value 1 pin P40 to P47, P50 to P55 total rms Peak value rms P01 to P03, P56, P57, IOLNote P60 to P67 total P01 to P03, P64 to P67 total Peak value rms Peak value rms Analog input pin P00 to P04, P10 to P17, P20 to P27, P30 to P37 P40 toP47, P50 to P57, P64 to P67, X1, X2, XT2 P60 to P67 Open-drain -0.3 to +16 -0.3 to VDD + 0.3 AVSS -0.3 to AVREF + 0.3 -10 -15 -15 30 15 100 70 100 70 50 20 50 20 -40 to +85 V V V mA mA mA mA mA mA mA mA mA mA mA mA mA C Test Conditions Rating -0.3 to + 7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to + 0.3 -0.3 to VDD + 0.3 Unit V V V V V
P10 to P17, P20 to P27, P30 to P37 Peak value total Operating ambient temperature Storage temperature TA rms
Tstg
-65 to +150
C
Note rms should be calculated as follows: [rms] = [peak value] x duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
33
PD78011H, 78012H, 78013H, 78014H
Capacitance ( TA = 25 C, VDD = VSS = 0 V )
Parameter Input capacitance I/O capacitance Symbol CIN Test Conditions f = 1 MHz Unmeasured pins returned to 0 V P01 to P03, P10 to P17, f = 1 MHz Unmeasured P20 to P27, P30 toP37, CIO pins returned to 0 V P40 toP47, P50 to P57, P64 to P67 P60 to P63 20 pF 15 pF MIN. TYP. MAX. 15 Unit pF
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics ( TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit
X1 X2 IC R1 C1 C2
Parameter Oscillator frequency (fX) Note 1 Oscillation stabilization time Note 2 Oscillator frequency (fX) Note 1 Oscillation stabilization time Note 2 X1 input frequency (fX) Note 1 X1 input high/low level width (tXH , tXL)
Test Conditions 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V After VDD reaches oscillator voltage range MIN. 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VDD = 4.5 to 5.5 V
MIN. 1 1
TYP.
MAX. 10
Unit
MHz 5 ms
4 1 1 10 5 10
Crystal resonator
X1
X2 IC
MHz
C1
C2
ms 30
External clock
X1
X2
1.0
10.0
MHz
PD74HCU04
45
500
ns
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wirinin the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. q Wiring should be as short as possible. q Wiring should not cross other signal lines. q Wiring should not be placed close to a varying high current. q The potential of the oscillator capacitor ground should be the same as VSS. q Do not ground wiring to a ground pattern in which a high current flows. q Do not fetch a signal from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.
34
PD78011H, 78012H, 78013H, 78014H
Subsystem Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit
XT1 XT2 IC R2 C3 C4
Parameter Oscillator frequency (fXT) Note 1 Oscillation stabilization time Note 2 XT1 input frequency (fXT) Note 1 XT1 input high/low level width (tXTH , tXTL)
Test Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
VDD = 4.5 to 5.5 V
1.2
2 10
s
External clock
XT1
XT2
32
100
kHz
5
15
s
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. q Wiring should be as short as possible. q Wiring should not cross other signal lines. q Wiring should not be placed close to a varying high current. q The potential of the oscillator capacitor ground should be the same as VSS. q Do not ground wiring to a ground pattern in which a high current flows. q Do not fetch a signal from the oscillator. 2. The subsystem clock oscillation circuit is a circuit with a low amplification level,more prone to misoperation due to noise than the main system clock. Particular care is therefore required with the wiring method when the subsystem clock is used.
35
PD78011H, 78012H, 78013H, 78014H
DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Input voltage high Symbol VIH1 Test Conditions P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-67 VIH2 P00-P03, P20, P22, P24-P27, P33, VDD = 2.7 to 5.5 V P34, RESET VIH3 P60-P63 (N-ch open-drain) VIH4 X1, X2 VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V Note Input voltage low VIL1 P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-67 VIL2 P00-P03, P20, P22, P24-P27, P33, VDD = 2.7 to 5.5 V P34, RESET VIL3 P60-P63 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 0 0 0 0 0 0 VIL4 X1, X2 VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V Note Output voltage high Output voltage low P01 to P03, P10 to P17, P20 to P27 P30 to P37, P40 to P47, P64 to P67 VOL2 SB0, SB1, SCK0 IOL = 400 A VOL1 VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA IOH = -100 A P50 to P57, P60 to P63 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA VDD = 4.5 to 5.5 V, open-drain pulled-up (R = 1 K) VOL3 0.5 V 0.2 VDD V 0.4 V 0 0 VIL5 XT1/P04, XT2 0 0 0 VDD - 1.0 VDD - 0.5 0.4 2.0 0.2 VDD 0.2 VDD 0.15 VDD 0.3 VDD 0.2 VDD 0.1 VDD 0.4 0.2 0.2 VDD 0.1 VDD 0.1 VDD V V V V V V V V V V V V V V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 0.8 VDD 0.8 VDD 0.85 VDD 0.7 VDD 0.8 VDD VDD - 0.5 VDD - 0.2 VIH5 XT1/P04, XT2 0.8 VDD 0.9 VDD 0.9 VDD 0 VDD VDD VDD 15 15 VDD VDD VDD VDD VDD 0.3 VDD V V V V V V V V V V V VDD = 2.7 to 5.5 V MIN. 0.7 VDD TYP. MAX. VDD Unit V
Note
When using XT1/P04 as P04, input the inverse of P04 to XT2 using an inverter. The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Remark
36
PD78011H, 78012H, 78013H, 78014H
DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Symbol VIN = VDD Test Conditions P00 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, RESET ILIH2 ILIH3 Input leakege ILIL1 current low VIN = 15 V VIN = 0 V X1, X2, XT1/P04, XT2 P60 to P63 P00 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, RESET ILIL2 ILIL3 Output leakage ILOH1 current high Output leakage ILOL current low Mask option pull-up resister Software pull-up resister R2 VIN = 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 15 40 90 k R1 VIN = 0 V, P60 to P63 20 40 90 k VOUT = 0 V -3 VOUT = VDD X1, X2, XT1/P04, XT2 P60 to P63 -20 -3 Note 3 20 80 -3 MIN. TYP. MAX. 3 Unit
Input leakage ILIH1 current high
A
A A A
A A A A
Note For P60-P63, if pull-up resistor is not provided (specifiable by mask option) a low-level input leak current of -200 A (MAX.) flows only during the 3 clocks (no-wait time) after an instruction has been executed to read out port 6 (P6) or port mode register 6 (PM6). Outside the period of 3 clocks following execution a read-out instruction, the current is -3 A (MAX.). Remark The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
37
PD78011H, 78012H, 78013H, 78014H
DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Supply current
Note 1
Symbol IDD1 10.00 MHz crystal
Test Conditions VDD = 5.0 V 10 % Note 2 VDD = 3.0 V 10 % VDD = 5.0 V 10 %
Note 3 Note 2
MIN.
TYP. 9.0 1.3 2.0 1.0 60 35 24 25 5 2 1 0.5
MAX. 18.0 2.6 4.0 2.0 120 70 48 50 15 10 30 10 10 30 10 10
Unit mA mA mA mA
oscillation operation mode IDD2 10.00 MHz crystal oscillation HALT mode IDD3 32.768 kHz crystal oscillation operation mode
Note 4
VDD = 3.0 V 10 % Note 3 VDD = 5.0 V 10 % Note 3 VDD = 3.0 V 10 % VDD = 2.0 V 10 %
Note 3 Note 4
A A A A A A A A A A A A
IDD4
32.768 kHz crystal oscillation HALT mode
VDD = 5.0 V 10 % Note 3 VDD = 3.0 V 10 % VDD = 2.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 %
Note 4 Note 4 Note 3 Note 4
IDD5
XT1 = VDD STOP mode when using feedback resistor
0.3 0.1 0.05 0.05
IDD6
XT1 = VDD STOP mode when not using feedback resistor
Notes 1. Current flowing into the VDD and AVDD pins. However, the current flowing into the A/D converter and internal pullup resistors is not included. 2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H) 3. When operating at low-speed mode (when the PCC is set to 04H) 4. When main system clock stopped.
38
PD78011H, 78012H, 78013H, 78014H
AC Characteristics (1) Basic Operation (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Operating on subsystem clock TI0 input frequency tTIH0 tTIL0 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 1.8 V VDD < 2.7 V TI1, TI2 input frequency TI1, TI2 input high/low-level width tTIL1 INTP0 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 1.8 V VDD < 2.7 V INTP1-INTP3, KR0-KR7 VDD = 2.7 to 5.5 V 1.8 2/fsam+0.1 Note 2/fsam+0.2 Note 2/fsam+0.5 10 20 RESET low level width tRSL VDD = 2.7 to 5.5 V 10 20
Note
Symbol TCY
Test Conditions Operating on main system clock 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 1.8 V VDD < 2.7 V
MIN. 0.4 0.8 2.0 40 2/fsam+0.1 2/fsam+0.2
Note Note
TYP.
MAX. 64 64 64
Unit
s s s s s s s
122
125
2/fsam+0.5 Note 0 0 4 275
fTI1
VDD = 4.5 to 5.5 V
MHz kHz ns
tTIH1
VDD = 4.5 to 5.5 V
100
s s s s s s s s
Interrupt input tINTH high/low-level width tINTL
Note In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible between fX/2N+1, fX/64 and fx/128 (when N= 0 to 4).
39
PD78011H, 78012H, 78013H, 78014H
TCY vs VDD (At main system clock operation)
60.0
10.0
Operation Guaranteed Range
Cycle Time TCY [ S]
5.0
1.0
0.5
0.1 0 1.0 1.8 2.0 2.7 3.0 3.5 4.0 5.0 5.5 6.0
Supply voltage VDD [V]
40
PD78011H, 78012H, 78013H, 78014H
(2) Read/Write Operation (TA = -40 to +85 C, VDD = 2.7 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD in external fetch Address hold time from RD in external fetch Write data output time from RD tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST tRDADH tRDWD VDD = 4.5 to 5.5 V Load resistor 5 k (0.5+2n)tCY+10 100 20 (2.5+2n) tCY -20 0.5tCY-30 1.5tCY-30 tCY-10 tCY 0.5tCY+5 0.5tCY+15 Write data output time from WR tWRWD VDD = 4.5 to 5.5 V 5 15 Address hold time from WR tWRADH VDD = 4.5 to 5.5 V tCY tCY RD delay time from WAIT WR delay time from WAIT tWTRD tWTWR 0.5tCY 0.5tCY tCY+40 tCY+50 0.5tCY+30 0.5tCY+90 30 90 tCY+60 tCY+100 2.5tCY+80 2.5tCY+80 0 (1.5+2n)tCY-20 (2.5+2n) tCY-20 0.5tCY 1.5tCY 0.5tCY (2+2n)tCY Test Conditions MIN. 0.5tCY 0.5tCY-30 50 (2.5+2n)tCY-50 (3+2n)tCY-100 (1+2n)tCY-25 (2.5+2n)tCY-100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. tCY = TCY/4 2. n indicates number of waits.
41
PD78011H, 78012H, 78013H, 78014H
(3) Serial Interface (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) (a) Serial Interface Channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK0 high/low-level width SI0 setup time (to SCK0) tKH1 tKL1 tSIK1 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V VDD = 4.5 to 5.5 V tKCY1/2-50 tKCY1/2-100 100 150 300 400 SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKSO1 C = 100 pF Note 300 ns tKSI1 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of SCK0 and SO0 output line. (ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK0 high/low-level width tKH2 tKL2 400 800 1600 2400 SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise, fall time tR2 tF2 When external device expansion function is used When external When 16-bit timer 700 ns tKSO2 C = 100 pF Note VDD = 2.0 to 5.5 V 300 500 160 ns ns ns tKSI2 tSIK2 VDD = 2.0 to 5.5 V 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
device expansion output function is function is not used used When 16-bit timer output function is not used 1000 ns
Note C is the load capacitance of SO0 output line. 42
PD78011H, 78012H, 78013H, 78014H
(iii) SBI mode (SCK0... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V MIN. 800 3200 4800 SCK0 high/low-level width SB0, SB1 setup time (to SCK0) tKH3 tKL3 tSIK3 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 100 300 400 SB0, SB1 hold time (from SCK0) SB0, SB1output delay time from SCK0 SB0, SB1 from SCK0 tKSB SCK0 from SB0, SB1 tSBK SB0, SB1 high-level width SB0, SB1 low-level width tSBL tKCY3 ns tSBH tKSO3 R = 1 k, C = 100 pF Note VDD = 4.5 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns tKSI3 tKCY3/2 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Note R and C are the load resistors and load capacitance of the SB0, SB1 and SCK0 output line.
43
PD78011H, 78012H, 78013H, 78014H
(iv) SBI mode (SCK0... External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V MIN. 800 3200 4800 SCK0 high/low-level width tKH4 tKL4 400 1600 2400 SB0, SB1 setup time (to SCK0) tSIK4 100 300 400 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 tKSB SCK0 from SB0, SB1 tSBK SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rise, fall time tR4 tF4 When external device expansion function is used When external When 16-bit timer 700 ns 160 ns tSBL tKCY4 ns tSBH tKSO4 R = 1 k, C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns
tKSI4
tKCY4/2
VDD = 4.5 to 5.5 V
0 0 tKCY4 tKCY4 tKCY4
300 1000
ns ns ns ns ns
device expansion output function is function is not used used When 16-bit timer output function is not used 1000 ns
Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
44
PD78011H, 78012H, 78013H, 78014H
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY5 Test Conditions R = 1 k, 2.7 V VDD 5.5 V MIN. 1600 3200 4800 SCK0 high-level width tKH5 VDD = 2.7 to 5.5 V tKCY5/2-160 tKCY5/2-190 SCK0 low-level width tKL5 VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V tKCY5/2-50 tKCY5/2-100 SB0, SB1 setup time (to SCK0) tSIK5 300 350 400 500 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSO5 0 300 ns tKSI5 600 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
C = 100 pF Note 2.0 V VDD < 2.7 V
Note R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
45
PD78011H, 78012H, 78013H, 78014H
(vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter SCK0 cycle time Symbol tKCY6 Test Conditions 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V MIN. 1600 3200 4800 SCK0 high-level width tKH6 650 1300 2100 SCK0 low-level width tKL6 800 1600 2400 SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSO6 R = 1 k, 4.5 V VDD 5.5 V 0 0 0 SCK0 rise, fall time tR6 tF6 When external device expansion function is used When external When 16-bit timer 700 ns 300 500 800 160 ns ns ns ns C = 100 pF Note 2.0 V VDD < 4.5 V tKSI6 tSIK6 VDD = 2.0 to 5.5 V 100 150 tKCY6/2 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
device expansion output function is function is not used used When 16-bit timer output function is not used 1000 ns
Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
46
PD78011H, 78012H, 78013H, 78014H
(b) Serial Interface Channel 1 (i) 3-wire serial I/O mode (SCK1... Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK1 high/low-level width SI1 setup time (to SCK1) tKH7 tKL7 tSIK7 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V VDD = 4.5 to 5.5 V tKCY7/2-50 tKCY7/2-100 100 150 300 400 SI1 hold time (from SCK1) SO1 output delay time from SCK1 tKSO7 C = 100 pF Note 300 ns tKSI7 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of SCK1 and SO1 output line. (ii) 3-wire serial I/O mode (SCK1... External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK1 high/low-level width tKH8 tKL8 400 800 1600 2400 SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO0 output delay time from SCK1 SCK1 rise, fall time tR8 tF8 When external device expansion function is used When external When 16-bit timer 700 ns tKSO8 C = 100 pF Note VDD = 2.0 to 5.5 V 300 500 160 ns ns ns tKSI8 tSIK8 VDD = 2.0 to 5.5 V 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
device expansion output function is function is not used used When 16-bit timer output function is not used 1000 ns
Note C is the load capacitance of SO1 output line.
47
PD78011H, 78012H, 78013H, 78014H
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK1 high/low-level width SI1 setup time (to SCK1) tKH9 tKL9 tSIK9 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V VDD = 4.5 to 5.5 V tKCY9/2-50 tKCY9/2-100 100 150 300 400 SI1 hold time (from SCK1) SO1 output delay time from SCK1 STB from SCK1 Strobe signal high-level width tSBD tSBW 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V tKCY9/2-100 tKCY9-30 tKCY9-60 tKCY9-90 Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYH 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 100 150 200 300 SCK1 from busy inactive tSPS 2tKCY9 ns ns ns ns ns tBYS 100 tKCY9/2+100 tKCY9+30 tKCY9+60 tKCY9+90 ns ns ns ns ns tKSO9 C = 100 pF Note 300 ns tKSI9 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of SCK1 and SO1 output line.
48
PD78011H, 78012H, 78013H, 78014H
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK1 high/low-level width tKH10, tKL10 400 800 1600 2400 SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time from SCK1 SCK1 rise, fall time tR10, tF10 When external device expansion function is used When external device expansion function is not used 1000 ns tKSO10 C = 100 pF Note VDD = 2.0 to 5.5 V 300 500 160 ns ns ns tKSI10 tSIK10 VDD = 2.0 to 5.5 V 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SO1 output line.
49
PD78011H, 78012H, 78013H, 78014H
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timing
1/fX tXL tXH
X1 Input
VIH4 (MIN.) VIL4 (MAX.)
1/fXT tXTL tXTH
XT1 Input
VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL0
tTIH0
TI0
1/fTI1 tTIL1 tTIH1
TI1,TI2
50
PD78011H, 78012H, 78013H, 78014H
Read/Write Operation External fetch (No wait):
A8-A15
Higher 8-Bit Address tADD1 Hi-Z Lower 8-Bit
Address
AD0-AD7 tADS tASTH ASTB
Operation Code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (Wait insertion):
A8-A15
Higher 8-Bit Address tADD1
AD0-AD7 tADS tASTH ASTB
Lower 8-Bit Address
Hi-Z tRDD1
Operation Code tRDADH tRDAST
tADH
RD tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
51
PD78011H, 78012H, 78013H, 78014H
External data access (No wait):
A8-A15 tADD2 AD0-AD7 tADS tASTH ASTB
Lower 8-Bit Address
Higher 8-Bit Address
Hi-Z tRDD2
Read Data
Hi-Z
Write Data
Hi-Z
tADH
tRDH
RD tASTRD WR tASTWR tWRL1 tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
External data access (Wait insertion):
A8-A15 tADD2 AD0-AD7 tADS tADH tASTH ASTB tASTRD RD tRDL2 WR tASTWR WAIT tRDWT2 tWTL tRDD2
Lower 8-Bit Address
Higher 8-Bit Address Hi-Z Hi-Z Hi-Z
Read Data
Write Data
tRDH
tRDWD
tWDS tWRWD tWRL1
tWDH
tWRADH
tWTRD tWRWT
tWTL
tWTWR
52
PD78011H, 78012H, 78013H, 78014H
Serial Transfer Timing 3-wire serial I/O mode:
tKLm tRn
tKCYm tKHm tFn
SCK0,SCK1
tSIKm
tKSIm
SI0,SI1
Input Data
tKSOm
SO0,SO1 m = 1, 2, 7, 8 n = 2, 8
Output Data
SBI mode (Bus release signal transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4
SB0, SB1 tKSO3, 4
SBI Mode (command signal transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tSIK3, 4 tKH3, 4 tF4
tKSB
tSBK
tKSI3, 4
SB0, SB1 tKSO3, 4
53
PD78011H, 78012H, 78013H, 78014H
2-wire serial I/O mode:
tKCY5,6 tKL5,6 tR6 SCK0 tKSO5,6 SB0, SB1 tSIK5,6 tKSI5,6 tKH5,6 tF6
3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK9,10 tKSO9,10
D1 tKSI9,10 tKH9,10 tF10
D0
D7
SCK1 tKL9,10 tKCY9,10 STB tR10 tSBD tSBW
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9
Note
10 tBYS
Note
10 + n tBYH
Note
1 tSPS
BUSY (Active High)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
54
PD78011H, 78012H, 78013H, 78014H
A/D converter characteristics (TA = -40 to +85 C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error Note 2.7 V AVREF AVDD 1.8 V AVREF 2.7 V Conversion time tCONV 2.0 V AVDD < 5.5 V 1.8 V AVDD < 2.0 V Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance tSAMP VIAN AVREF RAIREF 19.1 38.2 24/fX AVSS 1.8 4 14 AVREF AVDD Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 0.6 1.4 200 200 Unit bit % %
s s s
V V k
Note Overall error excluding quantization error (1/2 LSB). It is indicated as a ratio to the full-scale value. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85 C)
Parameter Data retention supply voltage Data retention supply current IDDDR VDDDR = 1.8 V Subsystem clock stop and feedback resister disconnected Release signal set time Oscillation stabilization wait time tSREL tWAIT Release by RESET Release by interrupt 0 2 /fX Note
18
Symbol VDDDR
Test Conditions
MIN. 1.8
TYP.
MAX. 5.5
Unit V
0.1
10
A
s
ms ms
Note In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/ fX and 215/fX to 218/fX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retension Mode Operating Mode
VDD STOP Instruction Execution
VDDDR
tSREL
RESET tWAIT
55
PD78011H, 78012H, 78013H, 78014H
Data Retention Timing (Standby Release Signal : STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Data Retension Mode Operating Mode
VDD
VDDDR STOP Instruction Execition
tSREL
Standby Release Signal (Interrupt Request) tWAIT
Interrupt Input Timing
tINTL INTP0-INTP2 tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
56
PD78011H, 78012H, 78013H, 78014H
12. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J
I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
Remark
Dimensions and materials of ES products are the same as those of mass-production products.
57
PD78011H, 78012H, 78013H, 78014H
64 PIN PLASTIC QFP (
14)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J
K
P
N
L P64GC-80-AB8-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Remark
Dimensions and materials of ES products are the same as those of mass-production products.
58
M
55
Q
PD78011H, 78012H, 78013H, 78014H
64 PIN PLASTIC LQFP (
12)
A B
48 49
33 32
detail of lead end
C
D
S
64
1
17 16
F
G
P
H
I
M
J K
N
NOTE
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.80.4 12.00.2 12.00.2 14.80.4 1.125 1.125 0.300.10 0.13 0.65 (T.P.) 1.40.2 0.60.2 0.15 +0.10 -0.05 0.10 1.4 0.1250.075 55 1.7 MAX. INCHES 0.5830.016 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.5830.016 0.044 0.044 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0550.008 0.024 +0.008 -0.009 0.006 +0.004 -0.003 0.004 0.055 0.0050.003 55 0.067 MAX. P64GK-65-8A8-1
Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
Remark
Dimensions and materials of ES products are the same as those of mass-production products.
M
Q
R
59
PD78011H, 78012H, 78013H, 78014H
13. RECOMMENDED SOLDERING CONDITIONS
The PD78011F/78012F/78013F/78014F/78015F/78016F should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our salespersonnel. Table 14-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD78011HGC-xxx-AB8 : PD78012HGC-xxx-AB8 : 64-Pin Plastic QFP (14 x 14 mm) 64-Pin Plastic QFP (14 x 14 mm) 64-Pin Plastic QFP (14 x 14 mm) 64-Pin Plastic QFP (14 x 14 mm)
PD78013HGC-xxx-AB8 : PD78014HGC-xxx-AB8 :
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Thrice max. Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Thrice max. Solder bath temperature: 260 C max. Duration: 10 sec. max. Number of times: Once Preliminary heat temperature: 120 C max. (Package surface temperature)
Recommended Condition Symbol IR35-00-3
VPS
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
Pin temperature: 300 C max., Duration: 3 sec. max. (per device side)
--
Caution Use more than one soldering method should be avoided (except in the case of partial heating).
60
PD78011H, 78012H, 78013H, 78014H
Table 14-1. Surface Mounting Type Soldering Conditions (2/2) (2) PD78011HGK-xxx-8A8 : 64-Pin Plastic LQFP (12 x 12 mm) PD78012HGK-xxx-8A8 : 64-Pin Plastic LQFP (12 x 12 mm)
PD78013HGK-xxx-8A8 : 64-Pin Plastic LQFP (12 x 12 mm) PD78014HGK-xxx-8A8 : 64-Pin Plastic LQFP (12 x 12 mm)
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Twice max., Number of days: 7 days Note (after that, 125 C prebaking for 10 hours is necessary.) < Points to note > Products packed in packing materials other than heat-resistant trays (such as magazines, taping, and non-heat resistance tray) cannot be baked while packed. Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Twice max., Number of days: 7 days Note (after that, 125 C prebaking for 10 hours is necessary.) < Points to note > Products packed in packing materials other than heat-resistant trays (such as magazines, taping, and non-heat resistance tray) cannot be baked while packed. Solder bath temperature: 260 C max. Duration: 10 sec. max. Number of times: Once, Preliminary heat temperature: 120 C max. (Package surface temperature), Number of days: 7 days Note (after that, 125 C prebaking for 10 hours is necessary.) Pin temperature: 300 C max., Duration: 3 sec. max. (per device side)
Recommended Condition Symbol IR35-107-2
VPS
VP15-107-2
Wave soldering
WS60-107-1
Partial heating
--
Note The number of days the device can be stored at 25 C, 65% RH MAX. after the dry pack has been opend. Caution Use more than one soldering method should be avoided (except in the case of partial heating). Table 14-2. Insertion Type Soldering Conditions
PD78011HCW-xxx : PD78012HCW-xxx : PD78013HCW-xxx : PD78014HCW-xxx :
64-Pin Plastic Shrink DIP (750 mil) 64-Pin Plastic Shrink DIP (750 mil) 64-Pin Plastic Shrink DIP (750 mil) 64-Pin Plastic Shrink DIP (750 mil)
Soldering Method Wave soldering (pin only) Partial heating
Soldering Conditions Solder bath temperature: 260C max., Duration: 10 sec. max.
Pin temperature: 300C max., Duration: 3 sec. max. (per pin)
Caution
Wave soldering is only for the lead part in order that jet solder can not contact with the chip directly.
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APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for the development of systems using the PD78014H subseries. Language processor software
RA78K/0 Notes 1, 2, 3, 4 CC78K0 Notes 1, 2, 3, 4 DF78014 Notes 1, 2, 3, 4, 6 CC78K0-L Notes 1, 2, 3, 4 Assembler package common to 78K/0 series C compiler package common to 78K/0 series Device file common to PD78014 subseries C compiler library source file common to 78K/0 series
Debugging tools
IE-78000-R IE-78000R-A Notes 8 IE-78000-R-BK IE-78014-R-EM-A EP-78240CW-R EP-78240GK-R EP-78012GK-R EV-9200GC-64 In-circuit emulator common to 78K/0 series In-circuit emulator common to 78K/0 series (for integrated debugger) Break board common to 78K/0 series Emulation board common to PD78018F and 78018FY subseries (VDD = 3.0 to 6.0 V) Emulation probe common to PD78244 subseries Emulation probe common to PD78018F subseries Socket mounted on printed wiring board of target system created for 64-pin plastic QFP (GC-AB8 type) TGK-064SBW Adapter mounted on printed wiring board of target system created for 64-pin plastic QFP (GK-8A8 type). This is a product of TOKYO ELETECH Corp. Consult NEC when purchasing this product. SM78K0 Notes 5, 6, 7 ID78K0 Notes 4, 5, 6, 7 SD78K/0 Notes 1, 2 DF78014 Notes 1, 2, 3, 4, 5, 6, 7 System emulator common to 78K/0 series Integrated debugger common to 78K/0 series Screen debugger for IE-78000-R Device file common to PD78014 subseries
Real-Time OS
RX78K/0 Notes 1, 2 MX78K0 Notes 1, 2 Real-time OS for 78K/0 series OS for 78K/0 series
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PD78011H, 78012H, 78013H, 78014H
Fuzzy Inference Devleopment Support System
FE9000 Note 1/FE9200 Note 6 FT9080 Note 1/FT9085 Note 2 FI78K0 Notes 1, 2 FD78K0 Notes 1, 2 Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM and compatible machine (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 series 300TM (HP-UXTM) based 4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-UX/V) based 5. PC-9800 series (MS-DOS + WindowsTM) based 6. IBM PC/AT and compatible machine (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based 8. Under development. Remarks 1. For development tools manufactured by a third party, refer to the 78K/0 Series Selection Guide (U11126E). 2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78014.
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PD78011H, 78012H, 78013H, 78014H
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name Document No. Japanese Planned to publish U11898J IEU-849 U10903J U10904J Planned to publish English Planned to publish This manual IEU-1372 -- -- --
PD78014H Subseries User's Manual PD78014 Data Sheet
78K/0 Series User's Manual - Instruction 78K/0 Series Instruction List 78K/0 Series Instruction Set
PD78014H Subseries Special Function Register List
Development Tools Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language CC78K/0 C Compiler Application Note CC78K Series Library Source File IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78014-R-EM-A EP-78240 EP-78012GK-R SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Components User Open Programming Know-how Document No. Japanese EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEA-618 EEU-777 EEU-810 U10057J EEU-867 EEU-962 EEU-986 EEU-5012 U10181J U10092J English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEA-1208 -- U11376E U10057E EEU-1427 U10418E EEU-1513 EEU-1538 U10181E U10092E
Interface
ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Deb IBM PC/AT (PC DOS) Based Reference Reference Guide Introduction Reference Introduction Reference U11151J U11539J U11649J EEU-852 EEU-816 EEU-5024 EEU-993 -- -- -- -- -- EEU-1414 EEU-1413
Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 64
PD78011H, 78012H, 78013H, 78014H
Embedded Software Documents (User's Manual)
Document Name 78K/0 Series Real-Time OS Fundamental Installation Technical 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System - Translator 78K/0 Series Fuzzy Inference Development Suport System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-921 EEU-1458 EEU-858 EEU-1441 Fundamental Document No. Japanese U11537J U11536J U11538J EEU-5010 EEU-829 EEU-862 English -- -- -- -- EEU-1438 EEU-1444
Other Documents
Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Device Guide for Products Related to Micro-Computer: Other Companies Document No. Japanese C10943X C10535J C11531J C10983J MEM-539 MEI-603 U11416J C10535E IEI-1209 C10983E -- MEI-1202 -- English
Caution
The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc.
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PD78011H, 78012H, 78013H, 78014H
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD78011H, 78012H, 78013H, 78014H
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
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PD78011H, 78012H, 78013H, 78014H
FIP and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM-DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a tradmark of SPARC International, Inc. SunOS is a tradmark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. Some related decuments are preliminary versions. This document, however, is not indicated as preliminary.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
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